BCM8155 ? multirate low-power 10g rz/nrz/duo-binary transceiver with 10g clock ? fully integrated multirate cdr, demux, mux, cmu ? 300-pin multisource agreement (msa) compatible ? compliant with itu gr-253, xfp, and sfp+ specifications ? 16-bit lvds interface compliant with optical internetworking forum (oif) sfi-4 ? programmable rz/nrz/duo-binary modes ? adjustable duty cycle in rz mode ? rx equalization for isi compensation ? limiting amplifier ? rx phase adjustment ? adaptable rx decision threshold adjustment ? 10g serial transmit clock output with adjustable phase ? 10g serial tx preemphasis ? prbs generator/checker fo r built-in self-test (bist) ? line and system loopback modes ? receiver and transmitter serial data polarity inversion ? lvds polarity inversion and bit order reversal ? analog loss-of-signal output (alosb) and loss-of-signal input (losib) ? cmu and cdr lock detect ? fifo overflow alarm ? reference clock: 1/16 or 1/64 of the line data rate ? selectable rx clock and rx data squelch ? selectable timing modes/cleanup are field-configurable ? internal phase detector and charge pump for cleanup phase- locked loop ( pll) (external vcxo required) ? broadcom serial control (bsc) interface compatible with philips ? i 2 c standard ? optional spi interface ? core voltage, 1v ? low power: 600 mw ? enhanced capability for long haul transmission with the ability to enable rz modulation on the transmitter ? compliant with oif, telcordia ? , itu-t, xfi specification, and ieee 802.3ae standards ? input sensitivity 10 mv peak-to-peak ? rates supported from 8.5 gbps to 11.352 gbps ? fault isolation with loopbacks, pattern generator, and checker ? reduces design cycle and time-to-market ? high-level of integration allows for higher port density solutions. ? lowest power sfi-4 to 10g serial transceiver ? standard cmos 65 nm fabrication process features summary of benefits ? oc-192/stm-64/10-gbe/fec transmission equipment ? sonet/sdh/10-gbe/10fc/fec for rz, nrz or duo- binary optical modules ? add/drop multiplexers ? digital cross-connects ? atm switch backbone ? sonet/sdh/10-gbe/10fc/fec for nrz, rz, or duo- binary test equipment ? terabit and edge routers applications
overview ? phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue, irvine, california 92617 ? 2008 by broadcom corporation. all rights reserved. 8155-pb00-r 11/21/08 broadcom ? , the pulse logo, connecting everything ? , and the connecting everything logo are among the trademarks of broadcom corporation and/or its aff iliates in the united states, certain other countries and/or the eu. any other trademarks or trade name s mentioned are the property of their respective owners. BCM8155 interface block diagram the BCM8155 is a fully integrated msa-compatible multirate sonet/ sdh/10-gbe/fibre-channel/fec transceiver operating at 8.5 gbps, 9.1 gbps, 9.953 gbps, 10.3125 gbps, 10.519 gbps, 10.664 gbps, 10.709 gbps, 11.095 gbps, 11.318 gbps, or 11.352 gbps. it supports rz, nrz, and duo-binary modulation formats. on-chip clock synthesis is performed by a high-frequency, low-jitter pll, allowing the use of a low-frequ ency reference clock selectable to the line rate divided by 16 or 64. the 10g tx clock phase adjusts for clocked driver applications. an on-chip phase detector and charge pump, plus external vcxo, implements a cleanup pll. this can attenuate jitter on the cdr- recovered clock for loop timing applications, or provide a low-jitter reference from a noisy system clock. sonet timing modes can employ the new BCM8155 architecture, making timing mode and cleanup functions user-selectable in the field rather than during manufacturing. this simplifies engineering and manufacturing requirements. the low-jitter lvds interface guarantees compliance with the bit error rate requirements of the telcordia (formerly bellcore), ansi, and itu- t standards. new features added to the BCM8155 include: ? selectable rz, nrz and db modulation ? rates from 8.5 gbps to 11.352 gbps ? prbs generator/checker for bist ? adaptive decision threshold adjustment ? adjustable 10g tx clock phase ? 10g rx equalization for isi compensation ? 10g tx preemphasis ? differential duo-binary precoder ? bsc interface (compatible with philips i 2 c standard) or optional spi interface the BCM8155 is offered in two different packages: 1. 12 mm x 12 mm, 196-pin bga (0.8 mm ball pitch) 2. 15 mm x 15 mm, 196-pin bga (1 mm ball pitch) system interface line interface txrefclkp/n rxrefclkp/n vcxop/n txpclkp/n txmclkp/n rxmclkp/n txpiclkp/n txdin[15:0]p/n rxpoclkp/n rxdout[15:0]p/n tsdp/n tsclkp/n rdinp/n txvcp/n rxvcp/n offsetp/n phdout rdincm auxp/n rb_cal rb_cal_vss txfifoerrb txlockerrb phdlockerrb alosb rxfifoerrb rxlockerrb resetb losib txrefsel spi_sel sda scl adr[2:0] +1.0v +1.8v +3.3v vss +1.0v differential externally ac-coupled internally biased +1.0v differential cml externally ac-coupled internally biased +1.0v lvds +1.0v lvds +1.8v/2.3v lvds +1.0v differential cml externally ac-coupled +1.0v differential cml externally ac-coupled internally biased +1.0v analog +3.3v analog connect 4.75-k resistor between these two pins +3.3v cmos +3.3v cmos open drain cmos reference clock inputs reference clock outputs transmitter parallel inputs receiver parallel outputs filter and bias inputs clean-up pll charge pump output resistor calibration reference status outputs control inputs bsc transmit serial outputs receive serial input auxillary input bypass
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